1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a number of memory cell transistors each of which is provided with a floating gate electrode and a control gate electrode, and a method of fabricating the same.
2. Description of the Related Art
Nonvolatile semiconductor memory devices such as NAND flash memories comprise a number of memory cell transistors each of which is provided with a floating gate electrode as a gate electrode. The floating gate electrode is disposed between two insulating films which are further disposed between a semiconductor substrate and a control gate. The floating gate electrode stores electrical charge so that the memory device can maintain a memorizable state even after power-off thereof.
A distance between cells adjacent to each other has recently been reduced for improvement in a degree of integration in the above-described NAND flash memories. On the other hand, an element isolation region is formed between the memory cell transistors adjacent to each other. With refinement in the design rules, a width of the region where the element isolation region is to be formed needs to be reduced. Accordingly, it has become difficult to bury an element isolation insulating film such as silicon oxide film in a trench having a high aspect ratio and a small opening width. In order to overcome the difficulty, Japanese patent application publication, JP-A-2006-269789, discloses a coating-type oxide film used as an element isolation insulating film for improvement in a trench-filling characteristic of an insulating film.
A coating-type oxide film used as an element isolation insulating film, such as polysilazane, contains impurities resulting from a solvent, such as carbon (C) or nitride (N). When the impurities remain in the film as fixed charge, off-leak current of a transistor is increased. In JP-A-2006-269789, a hafnia film or alumina film each of which has a film thickness of 5 nm is formed as a liner film for the polysilazane film, thereby cancelling a fixed charge to reduce off-leak current.
However, a new problem arises which cannot be overcome by JP-A-2006-269789. With reduction in the design rules, parasitic capacity is increased since gate electrodes of the memory cell transistors adjacent to each other are located close to each other. The adjacent memory cell transistors interfere with each other during operation due to the parasitic capacity. As a result, the memory cell transistors malfunction or a writing/erasing speed is reduced.
In order that interference between the adjacent memory cell transistors may be reduced, the parasitic capacity between the adjacent memory cell transistors needs to be reduced. For example, it is effective to reduce an area of an opposed portion of a gate electrode which is one of elements of the parasitic capacity. For this purpose, it has been suggested to reduce the height of the floating gate electrode. However, even the cell structure including the floating gate electrode with a reduced height necessitates the same coupling ratio as in the conventional configuration or a ratio of the capacity of tunnel insulating film (the first gate insulating film) to the capacity of interelectrode insulating film (the second gate insulating film), in order that a desired element characteristic may be ensured.
Thus, the reduction in the interelectrode insulation area is accompanied by the reduction in the height of the floating gate electrode as described above. The sidewalls of the floating gate electrode need to be utilized to the utmost extent in order that the reduction in the interelectrode insulation area may be compensated for. Accordingly, the location of the upper surface of the element isolation insulating film needs to be lowered as compared with the conventional configuration. However, a distance between the semiconductor substrate and the control gate electrode is reduced when the location of the upper surface of the element isolation insulating film is lowered. Accordingly, when high voltage is applied during writing, the electrical field intensity is rendered larger between the semiconductor substrate and the control gate electrode as compared with the conventional configuration, whereupon an amount of leak current is increased. As a result, a writing speed is reduced and the applied voltage cannot be raised to a desired threshold. Furthermore, electrically-charged atoms in the element isolation insulating film are diffused near to the side surfaces of the semiconductor substrate, forming fixed charge. As a result, the threshold voltage of the memory cell transistors varies.